Abdelrahman Esia

Participated in two successful tapeouts, contributing end-to-end design and layout responsibilities:

Tapeout 1:

• Designed and laid out multiple LDOs with different current capabilities (ranging from low-power standby to high-current operation).
• Conducted lab testing for the LDOs, including cold boot scenarios, power mode switching, and measurements of load and line regulation.

Tapeout 2:

• Designed and laid out a 2.4 GHz, 15 dBm Class AB Power Amplifier supporting multiple standards: Bluetooth Low Energy (BLE), Enhanced Data Rate (EDR), Basic Rate (BR), SparkLink, and HDT.
• Performed full EM simulations and layout of on-chip baluns.
• Conducted rigorous post-layout validation including PEX extraction and EM/circuit co-simulation.
• Designed a 14 dBm inverse Class D power amplifier for polar transmitters.
• Developed behavioral models for analog blocks using SystemVerilog for system-level integration and verification.
• Built custom shell scripts for netlist manipulation and layout debugging.
• Collaborated with system architects to meet aggressive timelines.

• Project: DDR54 PHY IP
  Macro: A 7-bit Resistive Ladder DAC
  Responsibilities:
  • Layout improvements to enhance the output Reference level Range.
  • Performance Verification by Developing Test-Benches (TBs) across many PVT corners and Running such TBs on a Post Layout Extracted Netlist with Monte Carlo.
  Project: DDR54 PHY IP
  Macro: A Two-stage Comparator
  Building Blocks:
  • Static Comparator implemented in Two Cascaded Stages
  • Folded Cascode Amplifier with Resistive Load
  • CML to CMOS Conversion Circuit
  • Constant-Gm Bias Generation as well as Current Distribution Circuits
  • Level Shifters
  Responsibilities:
  • Provide design solutions to Minimize the Delay of the comparator in order to enhance the data to clock skew.
  • Performance Verification by Developing Test-Benches (TBs) across many PVT corners and Running such TBs on a Post Layout Extracted Netlist with Monte Carlo.
  Project: DDR54 PHY IP
  Macro: A 4-tap Loop Unrolled DFE Receiver
  Building Blocks:
  • Static Comparator implemented in Three Cascaded Stages
  • Folded Cascode Amplifier with Resistive Load
  • PMOS Input Pair Amplifier with Resistive Load
  • CML to CMOS Conversion Circuit
  • Constant-Gm Bias Generation as well as Current Distribution Circuits
  • Level Shifters
  Responsibilities:
  • Provide design solutions to make the CML2CMOS circuit robust against mismatch/Process Variations and this was verified through Monte-Carlo Simulations.
  • Provide design solutions to Enhance the Data-Dependent Jitter (DDJ) of the Rx Macro.
  • Performance Verification by Developing Test-Benches (TBs) across many PVT corners and Running such TBs on a Post Layout Extracted Netlist with Monte Carlo.
  • Provide Layout Guidance/Rules to the Layout Engineer for Reducing undesired Effects (e.g. Mismatch/Crosstalk/Kickback Noise) and Optimizing Floorplan & Critical Routes.
  • Reliability Analysis: MOS Aging, ERC, Electromigration and IR drop.
  • Library Characterization (Liberty Files) (by using silicon-smart and Nano time tools) to be used by the Digital Implementation Team to Perform Static Timing Analysis (STA).

• Responsible for the floor planning and the physical layout of multiple macros in the IP on advanced technology nodes.
• Responsible for integrating all macros on the top-level.
• Responsible for the back-end verification checks including DRC, LVS, PEX, PERC, ERC, EMIR, and Antenna, and for fixing any related issues.
• Developed a DRC rule in SVRF format that checks for double connection for wide transistors.
• Responsible for developing scripts to automate the physical design flow.